BitBuster b.1

The b.1 edition (900-006-A) is the first development revision of the BitBuster. Most specification details are the same as the b.2 revision, but it contains a few hardware mistakes that were made during development.

The following issues were fixed in the subsequent revisions:

• the USB C port lacks the necessary resistors to support Power Delivery. This also affects a few samples of the b.2 edition (rev. 900-006-B)
• RTS/DTR are missing a connection to RESET_L and GPIO0. This results in the USB host not properly setting the bootmode for firmware download, essentially rendering the board unflashable.
• Due to wrong documentation in the ESP32-datasheet, the GPIO2 pin was stripped high, as it functions as the I2C clock line (DUT_SCL) for the DUT EEPROM. However, for the correct boot device to be selected (QSPI flash), this pin has to be strapped low. For b.2 the I2C clock line was moved to a different pin and this pin pulled low.
• PHY RESET_L is connected to an input-only GPIO pin, essentially rendering the PHY inoperative. The fix moved the line to a different pin.
• FPGA RESET_L is connected to an input-only GPIO pin, essentially rendering the PPGA inoperative. The fix moved the line to a different pin.
• Due to a datasheet error, the PHY’s mode strap for selecting MII/RMII mode for the interface to the ESP32 was wrongly selected. The fix is a simple pull-up.
• Two pins connecting the SPI flash to the ESP32 were crossed over, breaking dual IO mode in the QSPI interface.

Furthermore, the b.2 edition includes the following changes:

• Some LEDs had to be moved to the FPGA due to pin shortage on the ESP32, and made available to the ESP via the SPI interface of the FPGA.
• A reset button and a button for confirming OTA firmware updates were added on the input-only pins of the ESP.
• Some cosmetic changes in silkscreen labeling for the external inputs and LEDs.
• Additional test points for breaking out power lines.